Conventionally, various types of wiring substrates are proposed for mounting a semiconductor chip thereon.
For example, there is proposed a wiring substrate that includes a first wiring part having plural wiring layers, a second wiring part mounted on the first wiring part and having a thermal expansion rate smaller than that of the first wiring part, and a semiconductor chip mounted on the second wiring part and having a thermal expansion rate substantially equal to that of the second wiring part. Further, there is proposed a wiring substrate that includes a wiring pattern formed on a silicon substrate.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-270037    Patent Document 2: International Publication Pamphlet No. WO 05/114728
A wiring substrate for mounting a semiconductor chip thereon is desired to have a connection reliability that can endure stress caused by the difference of thermal expansion rates. It is also desired for the wiring substrate to be capable of forming narrow pitch external connection terminals (e.g., solder bumps) in correspondence with electrode terminals of the semiconductor chip.